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Silicon Labs /BGM240PB22VNA /RAC_S /SYNTHENCTRL

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Interpret as SYNTHENCTRL

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https://regviz.com/r/Silicon Labs/EFR32MG24A010F1536GM40/RAC_S/SYNTHENCTRL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (fast_start_up_0)VCOSTARTUP 0 (Disabled)VCBUFEN 0 (EnablePowerbleed)MMDPOWERBALANCEDISABLE 0 (LPFBWRX)LPFBWSEL

LPFBWSEL=LPFBWRX, VCBUFEN=Disabled, VCOSTARTUP=fast_start_up_0, MMDPOWERBALANCEDISABLE=EnablePowerbleed

Description

No Description

Fields

VCOSTARTUP

SYVCOFASTSTARTUP

0 (fast_start_up_0): undefined

1 (fast_start_up_1): undefined
VCBUFEN

SYLPFVCBUFEN

0 (Disabled): undefined

1 (Enabled): undefined
MMDPOWERBALANCEDISABLE

SYMMDPOWERBALANCEENB

0 (EnablePowerbleed): undefined

1 (DisablePowerBleed): undefined
LPFBWSEL

LPF bandwidth register selection

0 (LPFBWRX): Select LPFBWRX

1 (LPFBWTX): Select LPFBWTX

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data